Integrated circuits produced in SOI technology have a certain number of advantages. Such circuits generally have a lower power consumption for an equivalent performance. Such circuits also have lower parasitic capacitances, thereby allowing switching speeds to be improved. In addition, the phenomenon of latch up encountered in bulk technology MOS transistor may be prevented. Such circuits therefore prove to be particularly suitable for SoC or MEMS applications. It has also been observed that SOI integrated circuits are less sensitive to the effects of ionising radiation and thus prove to be more reliable in applications where such radiation may cause malfunctions, especially in space applications. SOI integrated circuits may notably comprise active SRAM memory or logic gates.
Many studies have focused on reducing the static consumption of logic gates while increasing their switching speed. Certain integrated circuits currently being developed incorporate both low-consumption logic gates and fast-access logic gates. To generate these two types of logic gates in a given integrated circuit, the threshold voltage of certain transistors of the fast-access logic gates is reduced and the threshold voltage of other transistors of the low-consumption logic gates is increased. In bulk technology, modulation of the threshold voltage level of transistors of the same type is achieved by modifying the doping level in their channels and by modulating the voltage applied to the well. However, in FDSOI (for fully depleted silicon-on-insulator) technology the doping of the channel is almost non-existent (1015 cm−3). Thus, the doping level of the channel of the transistors cannot vary substantially, thereby preventing the threshold voltages from being modified in this way. One solution proposed in certain studies, in order to produce transistors of the same type with different threshold voltages, is to use different gate materials in these transistors. However, in practice producing such an integrated circuit proves to be technically difficult and economically prohibitive. In order for different transistors produced in FDSOI technology to have different threshold voltages it is also known to use a biased ground plane placed between a thin insulating oxide layer (TBOX or UTBOX) and the silicon substrate. By adjusting the doping of the ground planes and their bias, a range of threshold voltages can be defined for the various transistors. It is thus possible to obtain transistors with low threshold voltages (called LVT transistors), transistors with high threshold voltages (called HVT transistors), and transistors with average threshold voltages (called SVT transistors). In order to allow the operation of the various transistors they must be electrically isolated from one another. Therefore the transistors are generally encircled by trench isolations called STIs (for “shallow trench isolations”) which extend as far as the wells. In a certain number of integrated-circuit configurations, it is necessary to provide additional trench isolations having a depth smaller than the depth of the aforementioned trench isolations.
It has thus been proposed to use these shallower trench isolations to bias ground planes via lateral contacts. The fabrication processes envisaged run the risk of degrading the UTBOX layer (this layer being highly sensitive due to its small thickness), shallower trench isolations may also provide lateral protection for the UTBOX layer so as thus to eliminate the risk of a short-circuit forming between the transistor and the substrate. These shallower trench isolations pass through the UTBOX layer but do not extend to the depth of the interface between the ground planes and the wells. In practice, forming trench isolations having two different depths proves to be problematic. This is because such a structure potentially requires fabrication processes that are substantially more complex or very different from proven fabrication processes.
Moreover, document US 2011/0057287 describes an integrated circuit produced in bulk technology. This document suggests placing memory cells and peripheral circuits into two separate zones. The trench isolations have different depths in these two zones.
The fabrication process proposed in this document is the following. A lower silicon oxide film is formed by thermal oxidation on a silicon substrate. A polysilicon film is formed on the lower silicon oxide film by a CVD process. A silicon nitride film is formed on the polysilicon film, for example by CVD. This silicon nitride film is covered with an upper silicon oxide film. A photolithography mask is produced, then an anisotropic etch or chemical etch is carried out with this mask in order to form trenches to a first depth in the silicon substrate, through the various films.
A photolithography mask is produced, which mask covers the trenches intended for the memory-cell zone while leaving the trenches intended for the peripheral circuit zone uncovered. This mask and the upper silicon oxide film serve as masks for an anisotropic etch so that the trenches intended for the peripheral circuit zone are etched for longer and are therefore deeper than the masked trenches. The mask is then removed so as to expose the shallower trenches. Silicon oxide is then deposited, for example using a PECVD process, in order to fill the various trenches. Next, this silicon oxide surface deposit and the upper silicon oxide film are removed by a CMP process.
For example by means of wet etching in orthophosphoric acid and then hydrofluoric acid, the silicon nitride film, the polysilicon film and the lower silicon oxide film are removed, exposing the silicon substrate. In this way, trench isolations of different depths, formed by a silicon oxide filling step, are obtained. Conventional bulk-processing operations are then used to form transistors in the memory-cell zone of the peripheral circuits.
Here, forming trench isolations with two different depths requires additional steps, having a non-negligible impact on the fabrication cost of such an integrated circuit. Moreover, removing the photolithography etching mask from the shallower trench isolations is difficult with available processes beyond a certain depth value. Furthermore, it is difficult to envisage how such a process could be adapted to fabrication of SOI integrated circuits, due to the risk that the very thin UTBOX layer or the upper part of the trench isolations will be degraded during formation of the transistors in the active layer or during implantation of the wells or ground planes, and in particular during steps of etching with hydrofluoric acid.